A chip structure for bare chip/flip chip mounting is known in which elements (a redistribution layer and a bump electrode) necessary for packaging on a wafer level. Such a chip structure is described in, for example, Japanese Patent Laying-Open Nos. 2000-243754 (PTD 1), 2010-192867 (PTD 2) and the like.
In the chip structure described in each of the above-described two publications, a passivation film is formed on a conductive layer to be an electrode pad, and an organic insulating film, a redistribution layer, a bump electrode, and the like are formed on that passivation film.